So a linear feed-back shift register (LFSR) is a shift register whose input bit is a linear function of its previous state. This is a rotating register, in which one of the Flip-Flops has a XOR as its input, an XOR among two or more outputs of the remaining Flip-Flops. The outputs connected to the XOR Gate are called TAP. There are two TAPs in the below figure.

The circuit can be initialized with a different seed from Null vector. In the upper Figure two of the three Flip-Flops are connected to the XOR, which is a input to the other Flip-Flop. Let’s suppose that all bits are initialized to ’1’ after the reset. At each clock cycle the rotation continues and runs a sequence of pseudo random bits on the Flip Flop’s outputs, which will be repeated at a given frequency. In this case the sequence will have a length of 7 as shown in the table.

It can be demonstrated that the length of sequence is 2n − 1. The sequence is often associated to a polynomial where the terms different from zero are those with a position corresponding to the TAP.In this case P = 1 + x2 + x3.
Applications of LFSRs include generating pseudo-random numbers, pseudo-noise sequences, fast digital counters, and whitening sequences. Both hardware and software implementations of LFSRs |

## 8-bit lfsr in vhdl

The top level entity is comprised of 2 input and 1 output ports. Input ports are clock and reset. Output port is an 8-bit number. Top level entity looks like the the one given in below figure. The picture is taken from top level RTL design in xilinx inc.

**00000001**“. If you now calculate manually the output by using equation Z=0(bit) XOR 2(bit) XOR 3(bit) XOR 4(bit). You will get same result as in the simulation below.

### LFSR vhdl code

**LFSR8**. After entity input output ports declaration its time to define the internal architecture of the linear feed back register.

In architecture i first defined the two signals(**currstate** and **nextstate**) of 8-bit length. These signals are playing a vital role in lfsr working. Their purpose is to hold the current state and next state. In the process part first the reset port is defined. If reset is ‘1’ high then current state is initialized “**00000001**“. Else if its a rising edge of clock then next state is assigned to current state. Note that the reset is asynchronous and process is sensitive to input clock and reset.

**feedback**signal. On the bases of the

**feedback**signal

**nextstate**is calculated. The statement

**Nextstate <= feedback & Currstate(7 downto 1)**is concatenating the new lsb(least significant bit) which is

**feedback**with the rest of the number. The

**&**operator in vhdl is used for concatenation purposes. The new state is assigned to the next state. While the current state is assigned to output in the next statement.

### LFSR VHDL test bench

Filed Under: Microcontroller Projects, VHDL